Semiconductor devices are, generally speaking, small electronic apparatus that are capable of storing and manipulating information in the form of electrical signals. Coupled with input and output mechanisms and a power source, these devices are used in the manufacture of many different kinds of electronic appliances such as personal computers, cellular telephones, personal digital assistants, and gaming devices. Consumer appliances such as these have become very popular, and their popularity has helped support technological advances that have lowered their cost and increased their performance and reliability. Small, portable appliances are especially popular, and the market demand for even smaller and more energy-efficient devices is a constant driver in the industry. The drive to make smaller and smaller semiconductor devices, however, poses many challenges for chip manufacturers.
Semiconductor devices are made by fabricating thousands of very small electrical components on a substrate made of semiconductor material, such as doped silicon. The components, such as transistors, capacitors, resisters, and diodes, are formed by selective deposition and removal of successive layers of conducting, insulating, and semiconductor material. These components are also interconnected by conductive structures in similar fashion to form the integrated circuits that are operable to perform the various functions required of the device. Note that the term ‘device’ is herein used generally to designate all, or a portion of, or sometimes more than one functional apparatus; the specific device being described in any particular embodiment, however, should be apparent from the context.
For example, a semiconductor chip is a small, typically square or rectangular piece of silicon or other suitable substrate material upon which one or more integrated circuits has been formed. When fabrication of these devices is complete, the chip is encapsulated in the familiar black plastic material, or some other suitable means of protection, and may be found mounted to the circuit boards inside most modern electronic appliances. The package protects the chip mechanically and electrically, and provides leads or conductive bumps or some other means of establishing an external connection with the integrated circuits formed on the chip.
To make their manufacture more efficient, chips are not typically fabricated one at a time. Rather, a large number of them are fabricated together on a substrate frequently known as a wafer. A wafer is a typically round, flat piece of semiconductor material that has been sliced from an ingot of silicon or some other suitable material. FIG. 1 is a plan view of a typical semiconductor wafer 10. Wafer 10 is populated with a large number of dice 12 that have been formed upon its surface 11 in the manner generally described above. The fabrication process is often automated and depends on very precise positioning of the wafer, so an orientation notch 13 is formed on the periphery of wafer 10. Other means of precision positioning may of course be used as well. The dice 14, 15, and 16 are individually referred to for purposes of illustration; though in many cases they and all of the other dice on the surface 11 of wafer 10 are identically constructed. When fabrication is complete, or largely so, each die is separated from those adjacent to it in a process known as dicing, or singulation. Each separated die may also be referred to as a chip, though the terms are often interchangeable.
One such chip is shown in more detail in FIG. 2. FIG. 2 is a perspective view of an exemplary chip 16. The integrated circuits formed on the chip 16 are not individually shown, but are instead referred to generally as active area 18. Active area 18 is surrounded by a seal ring 17, which helps to protected the components of active area 18 during the fabrication process and, especially, during singulation. A number of bond pads 20 are arrayed about active area 18 and are used for making connections to the different integrated circuits contained therein. As should be apparent, the bond pads 20 are relatively larger than the individual circuit components, which are very small and would otherwise be very difficult to connect to. The actual connection is generally made by interconnects or other conductive structures (not shown), often disposed on one or more layers beneath the surface 21. As mentioned above, once singulated, chips may be packaged for individual use.
More recently, however, it has also become common to place more than one chip in a single package. This may be used to assemble an SIP (system in package) product where each chip handles a different portion of the system's (or subsystem's) function, and reduced the need for mounting many different packages on the circuit board of an electronic appliance. When this is done, connections may be made between chips, that is, between the active areas on respective chips, in much the same fashion as the external connections are made. Bond wires or leads, for example, may be mounted to bond pads on two different chips, or to a separate enclosed device used solely for making connections. While SIPs and similar devices may offer considerable improvements in performance compared to systems contained in multiple packages and mounted on a circuit board, market demands are forcing manufacturers to seek out even more performance gains.
A 3D (three-dimensional) semiconductor device may offer such gains. In a 3D device, the separate chips to be packaged together are stacked one on top of the other in a configuration sometimes known as a SIC (stacked integrated circuit) package. One example of such a device is shown in FIG. 3. FIG. 3 is an elevation (side) view of an exemplary SIC 30. Note that FIG. 3 is not necessarily drawn to scale, and that only a portion of each of the separate components is shown. In this example, SIC 30 includes three chips 34, 36, and 38, which are mounted onto a base wafer 32. Inter-chip layers 33, 35, and 37 may include an adhesive or some other form of bonding mechanism. Base wafer 32 may be a functional device with its own active area or may simply be a device to interconnect the chips 34, 36, and 38. In this example, greatly simplified for clarity, three bond wires 39 are used to connect each of these chips to base wafer 32.
As should be apparent, the active areas formed on each chip are, in an 3D-SIC, much closer together than if the chips were mounted side by side, due to the relatively-thin vertical dimension of most chips. Designers may take further advantage of this by strategically laying out the various integrated circuits on each chip to even further reduce the distance between certain circuits that are to be interconnected. Situated in this manner, active areas may be coupled with each other through solid vertical structures called vias, which are narrow conductor-filled recesses formed in one of the chips, passing all of the way through to connect to a vertically-adjacent chip. An example of this is shown in FIG. 4.
FIG. 4 is a side view illustrating in cross-section an exemplary SIC 40. SIC 40, like SIC 30 shown in FIG. 3, includes multiple chips arranged in a 3D configuration. Chip 44 is mounted on base wafer 42 using an inter-chip layer 43, and chip 46 is mounted on chip 44 using an inter-chip layer 45. In SIC 40, however, the inter-chip electrical connections are made using vertical vias. Note that the term ‘vertical’ is used for convenience with reference to the orientation of SIC 40 in FIG. 4. In actual practice, the device will usually though not necessarily be fabricated largely while in this orientation, though the finished product need not remain oriented in any certain manner.
Returning to the example of FIG. 4, base wafer 42 has two contacts 51 and 52, which are externally-accessible conductors to which other devices may connect. There will normally be many more such structures, of course, in a typical SIC; only two are shown here for simplicity. These will be sometimes referred to as ‘target contacts’ to distinguish them from other features, though they may be used for multiple functions in an actual device. The target contacts 51 and 52 are presumably connected to active areas (not shown) formed on the surface of base wafer 42, or to other areas of interest. In many cases, the target contacts will be interconnects situated in a top metal layer of their respective device. In this SIC 40, target contacts 51 and 52 are coupled to, and usually bonded with, vias 64 and 65, respectively.
Vias 64 and 65 are actually conductor-filled vias, or narrow recesses, extending through chip 44. At their upper end, they connected to pads 74 and 75, respectively. Pads 74 and 75 are, in turn, connected to select integrated circuits (not shown) formed in an active area present on the upper surface of chip 44, or to other components or interconnect. Similarly, target contacts 53, 54, and 55 have been formed at the surface of chip 44 and are connected to integrated circuits formed there. When the SIC 40 is assembled, they are bonded with vias 61, 62, and 63 respectively. Vias 61, 62, and 63 meet, at their upper extremity, pads 71, 72, and 73. In this way, connections are made between active areas formed on different levels of the SIC40. Note, however, that although no bond wires or leads are shown in FIG. 4, they may of course be used in addition to the vias for inter-chip connections.
As should be apparent, the use of a three-dimensional configuration can greatly increase device performance characteristics, in large part by decreasing the distance signals must travel from one portion of the device to another. It also tends to reduce the horizontal area occupied by the finished chip or allow more components to be fabricated on the same size device. This smaller area does come in exchange for increased vertical height, but in many applications this dimension is less of a factor. The advantages of the three-dimensional configuration are enhanced when conductor-filled vias are used to establish connections between one chip and another within the semiconductor device. Unfortunately, current design and fabrication techniques often result in relatively lower yields compared to conventional practice.
Needed, then, is a way to exploit the advantages of three-dimensional semiconductor devices while increasing yield in the fabrication process by establishing more reliable inter-chip connections. The present invention provides just such a solution.